The present invention relates to a semiconductor device for generating a high potential, such as a word line potential, which is not less than the power voltage.
FIG. 13 is a schematic view of a semiconductor device of prior art.
Shown in FIG. 13 are a boosted potential generating circuit 1, a word line driver circuit 2, a row address buffer circuit 3, a row address decoding circuit 4, a sense amplifying circuit 5, and a memory cell array 6. In this semiconductor device of prior art, a signal of a high potential which has been supplied from the boosted potential generating circuit 1 and which is not less than the power voltage, is to be transferred to the word line driver circuit 2 to raise the potential of a word line selected by the row address decoding circuit 4, to the power voltage or more.
There is also disposed a level holding circuit 7. In an operational mode in which the potential of a word line is continuously raised for a long period of time (about several .mu. seconds), even though leak currents such as leak currents through transistors or the like, reduce the electric charge of a word line boosting signal 11 to be discussed later, the level holding circuit 7 compensates for such a reduction to prevent the word line potential from being reduced. Also shown in FIG. 13 are a drive signal control circuit 8, a starting signal 9, a row address signal 10 to be generated in the semiconductor device, the word line boosting signal 11, drive signals 12, 13, 14, 15, 16, n-channel MOS-type transfer transistors 17, 18, 19, 20, 21, 30, 31, gate electrodes 22, 23, 32 of the transfer transistors 19, 20, 31, a capacitor 24, a boosting terminal 25, a power source 26, a grounding 27, an excessive-boosting preventing circuit 28, a word line selecting signal 29, a word line 33, and a bit line 34. It is noted that the semiconductor device has a plurality of word lines and a plurality of bit lines, but only one word line and only one bit line are shown in FIG. 13.
A memory cell 35 is shown as one of a plurality of memory cells disposed in the memory cell array 6. There are also disposed an n-channel MOS-type selection transistor 36 and a capacitor 37. When the potential of the word line 33 is raised to the power voltage or more by the boosted potential generating circuit 1, the selection transistor 36 in the memory cell 35 is electrically conducted. This cancels a voltage drop corresponding to the threshold voltage in the selection transistor 36. Accordingly, the electric charge can efficiently be redistributed between the capacitor 37 and the bit line 34.
FIG. 14 is a schematic view of an example of the drive signal control circuit.
Shown in FIG. 14 are the starting signal 9, the drive signals 12, 13, 14, 15, 16, a delay device 81, a NAND 82, and inverters 83a, 83b, 83c, 83d, 83e, 83f, 83g, 83h, 83i. The delay times of these logic circuits 82, 83a to 83i form the timings for the drive signals 12, 13, 14, 15, 16. A booster 84 controls the potential of the drive signal 12 such that "H" is equivalent to Vcc+Vt and "L" is equivalent to Vcc.
When the starting signal 9 is activated at time T81, the following signals are activated in the following manner based on the respective delay times of the logic circuits 82, 83a to 83i and the delay device 81. That is, the drive signal 16 is activated to the "L" level at time T82, the drive signal 12 is activated to the "L" level at time T83, the drive signal 15 is activated to the "H" level at time T84, the drive signal 14 is activated to the "L" level at time T85, and the drive signal 13 is activated to the "H" level at time T86, and the operation of the boosted potential generating circuit 1 is controlled.
To prevent a plurality of word lines from being simultaneously selected in the word line driver circuit 2, the word line boosting signal 11 is required to be activated with a sufficient time allowance after the row address signal 10 internally generated by the starting signal 9 has been determined. In this connection, the delay device 81 is disposed for adjusting the timing at which the word line boosting signal 11 is activated.
With reference to FIGS. 15, 16, the following description will discuss the operation of the semiconductor device having the arrangement above-mentioned.
FIG. 15 shows the operational waveforms of main signals in the boosted potential generating circuit 1.
At the waiting state, the drive signal 13, the drive signal 15 and the gate electrode 23 are in the "L" level (0 V), the drive signal 14, the drive signal 16 and the boosting terminal 25 are in the "H" level (Vcc), the drive signal 12 is in the "H" level (Vcc+Vt), and the capacitor 24 is initially charged (difference in potential across the terminals=Vcc). The voltage off the gate electrode of the transfer transistor 18 is fixed to the power voltage. Accordingly, the potential of the gate electrode 22 is equal to "Vcc--threshold voltage" (hereinafter referred to as Vt), and the transfer transistor 19 becomes electrically conducted. At this time, the difference in potential between the gate and drain of the transfer transistor 18 (hereinafter referred to as Vgd) is 0 V. Accordingly, the gate electrode 22 is electrically disconnected from the drive signal 14.
When the starting signal 9 is activated, the drive signal 16 becomes the "L" level and the transfer transistor 21 which fixes the potential of the word line boosting signal 11 to the grounding potential, becomes electrically non-conducted.
Subsequently, when the drive signal 12 becomes the "L" level (=Vcc), the Vgd of the transfer transistor 17 which initially charges the capacitor 24 and which fixes the potential of the boosting terminal 25 to the power voltage, becomes 0 V such that the boosting terminal 2S is electrically disconnected from the power source 26.
When the drive signal 15 is raised to the "H" level (Vcc) at time T1a in the case where the power voltage is high, the transfer of electric charge to the gate electrode 23 through the transfer transistor 19 starts. At this time, the gate-source capacitance of the transfer transistor 19 (hereinafter referred to as Cgs) causes the potential of the electrically disconnected gate electrode 22 to be raised to a potential of Vcc+Vt or more with a rise in potential of the gate electrode 23 (hereinafter referred to as bootstrap effect). This results in cancellation of a voltage drop corresponding to Vt in the transfer transistor 19, causing the potential of the gate electrode 23 to be raised to Vcc. At this time, since the transfer transistor 20 becomes electrically conducted, the potential of the word line boosting signal 11 starts rising. At this time, the potential of the boosting terminal 25 is also lowered. With the potential drop of the boosting terminal 25, the difference in potential between the gate and source (hereinafter referred to as Vgs) in the transfer transistor 17 gradually increases. When the Vgs becomes not less than Vt, the transfer transistor 17 becomes electrically conducted. Accordingly, the potential of the boosting terminal 25 does not become Vcc-Vt or less.
When the potential of the drive signal 14 is brought to the "L" level (not greater than Vcc-Vt; 0 V in FIG. 15) at time T2a, the gate electrode 22 and the drive signal 14 are again electrically connected to each other through the transfer transistor 18. Thus, the potential of the gate electrode 22 becomes the "L" level (not greater than Vcc-Vt; 0 V in FIG. 15). At this time, the transfer transistor 19 becomes electrically non-conducted and the gate electrode 23 becomes electrically disconnected, as maintained at the Vcc level, from the drive signal 15.
When the drive signal 13 is raised to the "H" level (power voltage Vcc) at time T3a, the electric charge accumulated in the capacitor 24 is pushed out to the boosting terminal 25. Thus, the transfer of the electric charge to the word line boosting signal 11 through the transfer transistor 20 starts. At this time, the electric charge is redistributed between the capacitor 24 and the parasitic capacitance components such as the capacitances of the gates connected to the boosting terminal 25, such that the potential of the boosting terminal 25 is raised to a high potential of not less than Vcc+Vt. Further, the bootstrap effect in the transfer transistor 20 increases the potential of the gate electrode 23 to Vcc+2 Vt or more. This cancels a voltage drop corresponding to Vt in the transfer transistor 20 such that the word line boosting signal 11 can be driven to a high voltage identical with that of the boosting terminal 25.
FIG. 16 shows the operational waveforms of main signals in the word line driver circuit 2. In the word line driver circuit 2, the potentials of the word line selecting signal 29, the gate electrode 32 and the word line 33 are the "L" level (0 V). The potential of the gate electrode of the transfer transistor 30 is fixed to the power voltage Vcc level. Accordingly, when the word line selecting signal 29 is raised to the "H" level at time T1c, the gate electrode 32 is electrically charged up to the level Vcc-Vt and the transfer transistor 31 becomes electrically conducted. At this time, the Vgd of the transfer transistor 30 is equal to 0 V and the gate electrode 32 is electrically disconnected from the word line selecting signal 29. When there starts the transfer of the word line boosting signal 11 raised to not less than Vcc+Vt toward the word line 33 through the transfer transistor 31 at time T2c, the boot-strap effect in the transfer transistor 31 increases the voltage of the gate electrode 32 to not less than Vcc+2 Vt. This cancels a voltage drop corresponding to Vt in the transfer transistor 31 so that the word line 33 can be driven to a high potential identical with that of the word line boosting signal 11.
The following description will discuss the arrangement of the conventional level holding circuit 7 in FIG. 13. FIG. 17 is a schematic view of the conventional level holding circuit 7. Shown in FIG. 17 are a ring oscillator 901 having odd-number stages, an oscillation signal 902 supplied from the ring oscillator 901, N-type MOS transistors 903, 904, 905, a NAND circuit 906, a drive inverter 907, a capacitor 908 and an output terminal 909 connected to the word line boosting signal 11.
The following description will discuss the operation of the level holding circuit 7. Since the word line boosting signal 11 is in the "H" level (not less than Vcc+Vt), the ring oscillator 901 supplies the oscillation signal 902 in which "H" is equal to the power voltage Vcc and "L" is equal to 0 V. Further, since the word line boosting signal 11 is also connected to the gate electrode of the transistor 903, the transistor 903 is electrically conducted. Since the potential of the word line boosting signal 11 is not less than Vcc+Vt, the following equations are established in the transistor 903; EQU Vds=Vgs-Vt.gtoreq.(Vcc+Vt)-Vt =Power Voltage Vcc
wherein Vds refers to the difference in potential between the drain and the source.
Thus, the transistor 903 can transfer the electric charge without loss of voltage corresponding to Vt.
When the potential of the oscillation signal 902 is in the "H" level (=power voltage Vcc), that is, when the output of the drive inverter 907 is in the "L" level, the Vgs of the transistor 904 becomes not less than Vt, causing the transistor 904 to be electrically conducted. At this time, the gate electrode of the transistor 904 is connected to the power voltage Vcc. Accordingly, each of the gate electrodes of the capacitor 908 and the transistor 905 is electrically charged up to Vcc-Vt because the following equation is established in the transistor 904; EQU Vds=Vgs-Vt
At this time, the following equations are established in the transistor 905 ; EQU Vgs=(the gate potential of the transistor 905)-(the potential of the word line boosting signal 11)=(Vcc-Vt) -(Vcc+Vt or more).ltoreq.Vt
Accordingly, the transistor 905 is in the cutoff state.
On the other hand, when the potential of the oscillation signal 902 is in the "L" level (=0 V), that is, when the output of the drive inverter 907 is in the "H" level, the potential combined effect of the capacitor 908 raises the potential of the gate electrode of the transistor 905 to (Vcc-Vt)+Vcc=2 Vcc-Vt. At this time, when the Vgs of the transistor 905 is not less than Vt, the transistor 905 becomes electrically conducted and the electric charge accumulated in the capacitor 908 is supplied to the word line boosting signal 11 through the transistor 905. At this time, there is generated a loss of voltage corresponding to Vt in the transistor 905. Accordingly, the potential of the output terminal 909 becomes (2 Vcc-Vt)-Vt=2(Vcc-Vt). Further, the following equations are established in the transistor 904; EQU Vgs=Vcc-(2Vcc-Vt).ltoreq.Vt
Accordingly, the transistor 904 becomes in the cutoff state and the electric charge is not reversely transferred to the power source (Vcc).
Thereafter, when the potential of the oscillation signal 902 is brought again to the "H" level, the transistor 905 is cutoff to stop the supply of the electric charge and the transistor 904 becomes electrically conducted. Accordingly, the gate electrode of the transistor 905 and the capacitor 908 are electrically charged through the transistor 903. By repeating the cycle above-mentioned, the potential of the word line boosting signal 11 is maintained.
With reference to FIG. 17, the following description will discuss the inside arrangement of the excessive-boosting preventing circuit 28 in FIG. 13. In FIG. 17, the N-type MOS transistors are diode-connected to the word line boosting signal 11. Accordingly, the potential of the word line boosting signal 11 is clamped at a potential which is higher by n.times.Vt (wherein n refers to the number of stages of the N-type MOS transistors) than the power voltage Vcc. To lengthen the memory holding period of time in a memory device, it is more advantageous that Vt of each transistor of each memory cell is higher. Accordingly, the memory device uses transistors each having Vt which is higher than Vt of each transistor used in a peripheral circuit. Accordingly, the conventional excessive-boosting preventing circuit 28 is arranged such that the potential of the word line boosting signal 11 is clamped using transistors used in the peripheral circuit.
Nowadays, with the demand For a lower voltage power source, there is strongly desired a circuit to be operated with low power consumption.
In the conventional semiconductor device, however, when provision is made to provide a lower voltage power source without the threshold voltage Vt lowered, this increases the rate of the threshold voltage of each transistor with respect to the power voltage Vcc. Accordingly, the initial potential=Vcc-Vt of the gate electrode 22 becomes very small (for example, when it is supposed that Vt is equal to 0.7 V at the time the power voltage Vcc is equal to 1.5 V, the value of Vcc-Vt becomes 0.8 V). As a result, the following problems arise.
With reference to FIG. 15, the following description will discuss the operation of the boosted potential generating circuit 1 when the power voltage is low.
At the waiting state, each of the drive signal 13, the drive signal 15 and the gate electrode 23 is in the "L" level (0 V), and each of the drive signal 12, the drive signal 14, the drive signal 16 and the boosting terminal 25 is in the "H" level (power voltage Vcc). Since the voltage of the gate electrode of the transfer transistor 18 is fixed to the power voltage, the potential of the gate electrode 22 becomes Vcc-Vt.
When provision is made to provide a low voltage power source without the threshold voltage Vt lowered, the potential of the gate electrode 22 becomes very small. This lowers the transfer transistor 19 in current drive ability. In the extreme case, the transfer transistor 19 is caused to be electrically non-conducted.
Accordingly, even though the drive signal 15 is raised to the "H" level (power voltage Vcc) at time T1b, the potential of the gate electrode 23 cannot be raised to the power voltage Vcc. As a result, simultaneously when the drive signal 14 is brought to the "L" level at time T2b, the potential of the gate electrode 22 is brought to the "L" level through the transfer transistor 18 to cause the transfer transistor 19 to be electrically non-conducted. Thereafter, when the drive signal 13 is raised to the "H" level (power voltage Vcc) at time T3b, the potential of the boosting terminal 25 is raised to a high potential of Vcc+Vt or more and the electric charge is transferred to the word line boosting signal 11 through the transfer transistor 20. However, since the potential (Vcc-Vt) of the gate electrode 23 of the transfer transistor 20 is very small, the rise in potential of the gate electrode 28 due to the bootstrap effect in the transfer transistor 20 is insufficient. Accordingly, there are instances where Vgs in the transfer transistor 20 is not greater than Vt with the rise in the source potential (word line boosting signal 11) of the transfer transistor 20. This causes the transfer transistor 20 to be electrically non-conducted, thus preventing the word line boosting signal 11 from being driven to a potential identical with that of the boosting terminal 25.
With reference to FIG. 16, the following description will discuss the operation of the word line driver circuit 2 when the power voltage is low.
At the waiting state, each of the potentials of the word line selecting signal 29, the gate electrode 32 and the word line 33 is in the "L" level (0 V). The potential of the gate electrode of the transfer transistor 80 is fixed to the power voltage Vcc level. Accordingly, when the word line selecting signal 29 is raised to the "H" level at time T1d (T1c), the gate electrode 82 is electrically charged up to the level Vcc-Vt. Likewise in the boosted potential generating circuit 1, when provision is made to provide a low voltage power source without the threshold voltage Vt lowered, the potential of the gate electrode 82 becomes very small. This lowers the transfer transistor 81 in current drive ability. In the extreme case, the transfer transistor 81 is caused to be electrically non-conducted. As a result, even though the word line boosting signal 11 raised to Vcc+Vt or more is transferred at time T2d, this signal cannot disadvantageously be transferred to the word line 33.
Thus, the problems encountered in the boosted potential generating circuit 1 and the word line driver circuit 2 have been discussed. Such problems are present in any signal transmitting device having the common arrangement of the circuits 1 and 2, in which when the starting signal 9 (first signal) is generated, a second signal (for example, a signal at the boosting terminal 25 in the boosted potential generating circuit 1 or a word line boosting signal in the word line driver circuit 2) is transmitted to the outside as a third signal (for example, as a word line boosting signal in the former circuit 1 or as a signal for boosting the word line 33 in the latter circuit 2) because of electrical conduction of a first transistor (for example, the transistor 19 in the former circuit 1 or the transistor 31 in the latter circuit 2).
In the conventional level holding circuit 7, when provision is made to provide a low power voltage Vcc without Vt lowered, the following problems arise.
For example, when the power voltage Vcc is equal to 5 V and Vt is equal to 1 V, the following equations are established in the transistor 905; EQU Vg=2Vcc-Vt=2.times.5V-1V=9V
wherein Vg refers to the gate potential.
When the power voltage Vcc is equal to 5 V, the word line boosting signal 11 is raised to about 7.5 V. However, when it is supposed that the word line boosting signal 11 has been reduced in potential to about 6 V due to leak currents or the like, the following equations are established; EQU Vgs=9V-6V.gtoreq.Vt
Accordingly, the electric charge is supplied through the transistor 905 such that the potential of the word line boosting signal 11 can be restored to 2(Vcc-Vt)=2.times.(5-1) =8 V. When the power voltage Vcc is equal to 3 V and Vt is equal to 1 V, Vg in the transistor 905 becomes equal to 5 V. Here, it is supposed that the potential of the word line boosting signal 11 is normally about 4 or 5 V but has been reduced to about 3 V due to leak currents or the like. Through the transistor 905, the potential of the word line boosting signal 11 is restored to 2(Vcc-Vt)=2.times.(3-1)=4 V, which is still lower than the initial potential. More specifically, when provision is made in the conventional level holding circuit 7 to provide a lower power voltage Vcc without Vt lowered, the charge feed ability is disadvantageously insufficient.
Further, when the threshold voltages Vt of transistors in memory cells and peripheral circuits vary with process variations in the conventional excessive-boosting preventing circuit 28, there are instances where the degree of operational allowance is remarkably reduced because the varying manners are different from one another. For example, it is supposed that when the power voltage Vcc is equal to 3.6 V, the threshold voltage of the selection transistor 86 (hereinafter referred to as Vt(MC)) when reading "1" from the memory cell 35, is equal to 1.4 V. In this case, the potential required for the word line 33 is not less than Vcc+Vt(MC)=5.0 V. On the other hand, the potential of the word line boosting signal 11 is determined by a clamping potential of the excessive-boosting preventing circuit 28. Since the clamping potential is equal to Vcc+2 Vt which is equal to 3.6 V+2.times.0.8 V which is equal to 5.2 V, it can be said that the potential of the word line 33 is sufficient. Here, it is supposed that Vt(MC) becomes equal to 1.5 V (a rise by 0.1 V as compared with the standard) and Vt becomes equal to 0.1 V (a decrease by 0.1 V as compared with the standard) due to variations of process conditions. In this case, the potential required for the word line 33 is not less than 5.1 V. On the other hand, the potential of the word line boosting signal 11 is actually equal to 5.0 V. Thus, the word line 33 is insufficient in potential.